Actually I was thinking custom SOI. Doing a few hundred thousand
parallel circuits for this would be most cost-prohibitive if it were
in components rather than printed form, and virtually worthless from a
resale standpoint due either to the very low count of base pairs it
would be able to synthesize or incredible costs per chip.
On Jan 18, 4:34 pm, John Griessen <j...@industromatic.com> wrote:
> On 01/18/2012 09:19 AM, CoryG wrote:> On another note: is anyone here experienced with chip design
> > (semiconductor ICs)?
>
> Yes, I've done that for a few years, both logic design and analog and power layout.
>
> You're wanting an arrangement of circuits as in chip design, but not a custom
> silicon MOS or SOI chip I hope -- the ante money is very high. The free tools
> icarus verilog and gschem and pcb work well enough to do repeated elements
> in a layout and keep it exact so you can simulate the overall with iverilog.
> The machine you want is to load a sequence and have the analog volt controlled
> reaction chambers do your bidding for as many BPs at a time as you can, right?
>
> John
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